The present invention relates to a phase-locked loop (PLL) arranged to facilitate changing of the output frequency to a desired frequency. The present invention also relates to a method of changing the output frequency of a PLL.
Typically, a PLL comprises a charge pump, a phase comparator for controlling the charge pump to conduct for a time equal to the phase difference between a comparison frequency signal and feedback signal, a loop filter for filtering the output of the charge pump to output a control voltage, a voltage-controlled oscillator (VCO) for outputting an output signal having a frequency controlled by the control voltage output from the loop filter, and a feedback loop for feeding back the output signal to the phase comparator as said feedback signal and including a feedback frequency divider for frequency the signal on the feedback loop.
In a single-loop, integer-N PLL, the charge pumped onto the loop filter is set entirely by the transient error ratio between the current frequency and the desired output frequency. The conduction time of the charge pump generating the transient is entirely controlled by the dynamics of the closed loop. The PLL is an example of a sampled data control system which will display xe2x80x9cinertiaxe2x80x9d under transient conditions due to charge transfer between the capacitors in the loop filter, typically an integration capacitor and a damping capacitor. As a result of this inherent inertia in the feedback loop, the control voltage is caused to overshoot the desired steady state value so that additional time is required for the control voltage and hence the frequency of the output signal to settle. Therefore, there is ringing in the control voltage until the loop servos out the error introduced by the control voltage overshooting, as the control voltage converges on its steady state value. This settle time of the loop to a particular error, known as its lock time is determined by the loop filter component values.
The present invention is intended to provide a PLL which minimises the settle time whilst maintaining a circuit structure which is easily implemented and reliable.
Attempts to date to decrease the settle time have relied upon increasing the magnitude of the charge pump gain to achieve an increase in the charge dumped onto the loop. However, such increase in the charge pump gain can cause instability in the loop dynamics. Attempts have been made to stabilise a higher gain mode by switching in additional damping in the loop filter. However, this is not desirable in an integrated solution as the need to switch additional damping capacitors and resistors increases the pin count of the IC card implementing the PLL. Furthermore, such switching in itself can cause problems as any switch inevitably has capacitance. Therefore, whilst such PLLs are effective to reduce the settle time somewhat, it would be desirable to produce the settle time further and to provide a more convenient PLL implementation.
According to a first aspect of the present invention, there is provided a method of operating a phase-locked loop comprising: a charge pump; a phase comparator for controlling the charge pump to conduct for a time equal to the phase difference between a comparison frequency signal and feedback signal; a loop filter for filtering the output of the charge pump to output a control voltage; a voltage-controlled oscillator for outputting an output signal having a frequency controlled by the control voltage output from the loop filter; and a feedback loop for feeding back the output signal to the phase comparator as said feedback signal and including a feedback frequency divider for frequency the signal on the feedback loop; the method comprising changing the frequency of the output signal by:
for a first period having a predetermined length, controlling the conduction time of the charge pump to place an amount of charge on the loop filter during the first period sufficient to produce a control voltage for controlling the voltage-controlled oscillator to output an output signal substantially at the desired output frequency; and
subsequently operating the phase-locked loop with a feedback frequency division ratio set to a proper value for locking the output frequency to the desired frequency.
According to a second aspect of the present invention there is provided a phase-locked loop comprising: a charge pump; a phase comparator for controlling the charge pump to conduct for a time equal to the phase difference between a comparison frequency signal and feedback signal; a loop filter for filtering the output of the charge pump to output a control voltage; a voltage-controlled oscillator for outputting an output signal having a frequency controlled by the control voltage output from the loop filter; and a feedback loop for feeding back the output signal to the phase comparator as said feedback signal and including a feedback frequency divider for frequency the signal on the feedback loop; wherein the phase-locked loop further comprises means for changing the frequency of the output signal to a desired frequency, comprising:
means for controlling the conduction time of the charge pump during a first period having a predetermined length to place an amount of charge on the loop filter during the first period sufficient to produce a control voltage for controlling the voltage controlled oscillator to output an output signal substantially at the desired output frequency; and
means for setting the feedback frequency division ratio to a proper value such that subsequent operation of the phase-locked loop locks the output frequency to the desired frequency.
Accordingly, the present invention allows the settle time to be increased by maintaining the slew rate of the loop filter at a high value during the first period. In other words, the present invention accelerates the provision of an appropriate amount of charge to the loop filter it may be termed a xe2x80x9ccharge acceleratorxe2x80x9d. In particular, this is done by controlling the conduction time of the charge pump to place an amount of charge on the loop filter sufficient to produce the necessary change in the control voltage provided to control the VCO. This allows the change to be placed on the loop filter more rapidly. In contrast the known PLLs require a large number of charge pump pulses to traverse the desired change in output frequency when the loop is operated normally by immediately setting the feedback frequency division ratio to its proper value for changing the output frequency.
Preferably at the end of the first period the feedback loop is opened for a second period to allow the control voltage output from the loop filter to settle and subsequently the feedback loop is closed.
In the second period, the charge pump is disabled to allow the control voltage on the loop filter to settle. During this time charge shuffles between the capacitors in the loop filter. For example, if the loop filter has an integration capacitor and a damping capacitor, charge may shuffle from the integration capacitor to the damping capacitor causing a slight decay in the control voltage. The overall settle time of the PLL is reduced if the charge pump is disabled in the second period, because the correct amount of charge has already been placed on the loop filter. If the feedback loop were closed during this period, the charge pump would cause additional amounts of charge to be pumped onto the loop filter. Although, through the feedback in the PLL, such charge pump pulses would eventually drive the control voltage to the desired value, the settle time would be increased.
Opening the feedback loop for the second period is preferred to reduce the settle time of the PLL, particularly if the first period is a single pulse. However it is not essential and is of less importance when the first period consists of plural control pulses because in that case the loop settles between each of the control pulses.
Subsequently, the loop is closed once again and the PLL operated normally with the feedback frequency division ratio set to the proper value necessary to lock the output frequency to the desired frequency.
The present invention allows the use of a charge pump which outputs a current having a fixed amplitude. Keeping the charge pump gain constant in this way allows the loop dynamics to remain predictable and therefore prevents instability.
Similarly, the present invention allows the dynamics of the loop filter to be maintained constant. Therefore, switching is avoided during the initial ramping of the loop filter voltage which avoids the problems associated with providing switching in the loop filter.
Preferably during the first predetermined period, the conduction time of the charge pump is controlled by operating the phase-locked loop with a feedback frequency division ratio set to an initial value other than the proper value. This provides a simple and convenient way of controlling the conduction time. For example, the initial value of the feedback frequency division ratio may be stored in a shadow register and supplied to the feedback frequency divider in sequence with the proper value stored in a main register.
The initial value may be determined based on the capacitance of the loop filter, the amplitude of the current output by the charge pump and the gain of the VCO.
Preferably, the first period is found by counting a first predetermined number of comparison periods of the phase comparator, for example by counting the reset pulses of the phase comparator.
To minimise the settle time, the first period is one comparison period of the phase comparator. By placing a sufficient amount of charge on the loop filter over a single comparison period the control voltage is changed as quickly as possible.
However, in a low voltage application, for example a mobile telephone, the charge pumps have a limited voltage headroom. In such a case, it is necessary for the first period to be a plural number of comparison periods, typically 10 to 20 periods. This minimises the voltage headroom required by the charge pumps, thereby allowing a low voltage application to traverse the change in output frequency in a minimum number of comparison periods.
Advantageously, the second period is determined by counting a second predetermined number of comparison periods of the phase comparator. This provides a simple method of determining the second period. The number of circuit elements can be reduced by using the same counter means as for counting the first period.